Strained silicon is widely viewed as an important technology for obtaining desired advancements in integrated circuit performance. Mobility enhancement results from a combination of reduced effective carrier mass and reduced intervalley (phonon) scattering. n-channel MOS field effect transistors (FET) achieve improved performance with induced biaxial tensile stress in the top silicon layer along both the width and length axes of the active area. p-channel MOSFETs exhibit improved performance with induced uniaxial tensile stress in the top silicon layer along the width axis only (transverse tensile stress). p-channel MOSFETs also exhibit improved performance with induced uniaxial compressive stress in the top silicon layer along the length axis only (longitudinal compressive stress). Compressive stress can be provided selectively in a silicon surface layer, for example, by using selective epitaxial SiGe stressors in the source and drain regions of a MOSFET to induce a desired compressive stress along the length axis (longitudinal).
Strained silicon is conventionally obtained by first growing a thick layer of silicon germanium alloy (SiGe) on a silicon substrate. The SiGe layer is grown to a sufficient thickness that the SiGe layer is relaxed to an unstrained condition at its surface. The in-plane lattice parameter of the SiGe surface is similar to that of a bulk crystal of SiGe of the same composition. SiGe alloys have larger lattice parameters than silicon. Hence the relaxed surface of the SiGe layer provides an in-plane lattice parameter larger than that of silicon. A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the SiGe layer. The thin epitaxial layer of silicon assumes the larger in-plane lattice parameter of the SiGe and grows in a strained state with bonds in the crystal lattice elongated in the growth plane. This approach, sometimes known as substrate-strained silicon or “virtual substrate” technology, grows a thin pseudomorphic layer of strained silicon on the relaxed surface of a SiGe layer.
So long as the strained silicon layer does not exceed a “critical thickness” for strain relaxation and some care is taken, the tensile strain is maintained in the strained silicon layer through the various implantation and thermal processing steps typical of CMOS manufacturing.
The use of relaxed SiGe as a “virtual substrate” to strain a subsequently deposited epitaxial silicon layer inevitably requires acceptance of a very high dislocation density in the SiGe layer because the SiGe relaxation mechanism is plastic in nature. In other words, relaxation in the SiGe layer occurs through the generation of strain-relieving misfit dislocations. A thin SiGe layer of suitable germanium concentration grown epitaxially on a silicon substrate is not strain relaxed and exhibits few misfit dislocations if the SiGe layer is not thicker than a “critical thickness” at which misfit dislocations are generated. On the other hand, if the SiGe layer is thicker than the “critical thickness,” the strained SiGe lattice undergoes plastic deformation and most or all of the misfit strain is relieved by the nucleation and propagation of misfit dislocations. Some fraction of the resulting misfit dislocations gives rise to threading dislocations (at least 104-105 cm−2) which propagate through the overlying strained silicon layer. Threading dislocations represent extended defects and give rise to multiple undesirable consequences in MOSFETs including source/drain junction leakage, reduction of channel mobility, variability of threshold voltage and enhanced diffusion paths leading to potential drain-to-source shorting in short-channel MOSFETs.
Silicon-on-insulator wafers afford certain advantages over conventional bulk silicon wafers and are gaining in importance in CMOS manufacturing. An SOI wafer may, for example, have a layer of silicon on top of a layer of insulator. In silicon-on-sapphire (SOS) technology, the insulator is a wafer of sapphire (crystalline aluminum oxide). Commercial exploitation of SOS is rather limited due to high wafer costs, limited wafer diameters and supply. SOI with a buried oxide layer between the top (active) silicon structure and an underlying crystalline silicon host or ‘handle’ wafer is the preferred SOI configuration for CMOS applications. The buried oxide (typically abbreviated to “BOX”) layer structure may be formed by high dose implantation of oxygen and annealing (accomplished, for example, using the so-called SIMOX process). The BOX layer may also be formed by wafer bonding a layer of silicon from a donor wafer to a BOX layer on a handle wafer. The bonded thin silicon layer may be separated from the donor wafer by subjecting the donor wafer to hydrogen ion implantation prior to bonding to create a defect layer at a depth corresponding to the desired thickness of the thin silicon layer and subsequently applying a force to laterally section the silicon on insulator wafer structure along the plane of the damage layer and so separate the silicon on insulator wafer from the donor wafer. An example of a process that forms BOX layers by this method is described in U.S. Pat. No. 6,372,609. Wafers manufactured according to the Smart Cut process are commercially available from Soitec, Inc., of Bernin, France. The BOX layers of conventional SOI wafers are not compressively stressed.
If the silicon layer on top of the BOX layer is thicker than approximately 50 nm, the silicon layer will not be fully depleted in normal operation of CMOS transistors. Such wafers are known as partially-depleted SOI. If the silicon layer on top of the BOX layer is thinner than approximately 50 nm, the silicon layer may be fully depleted in normal operation of CMOS transistors and such wafers are known as fully-depleted SOI (also known as ultra-thin body SOI). Ultra-thin body, fully depleted MOSFETs fabricated in ultra-thin SOI have multiple beneficial features which each contribute to improved transistor and integrated circuit performance including low sensitivity to semiconductor body doping, low source and drain junction capacitances, improved electrical isolation between neighboring MOSFETs and improved control of short channel effects.
A fully depleted SOI technology in which the semiconductor active regions have in-plane tensile strain could have the combined benefits of ultra-thin body semiconductor-on-insulator and of strained silicon. Various approaches to obtaining “strained silicon on insulator” have been described. U.S. Pat. No. 7,534,701 to Ghyselen, et al. describes a strained silicon-on-insulator manufacturing method wherein a blanket strained silicon layer is first formed on a relaxed surface of single crystal silicon germanium and subsequently bonded to a handle wafer with an oxide layer such that the strained silicon layer is transferred to the handle wafer. The tensile strain is retained in the thin strained silicon layer after separation of the silicon germanium, for example, by the previously described SmartCut process.
U.S. Pat. No. 6,372,609 to Wristers, et. al., describes forming an SOI wafer with a buried, compressively stressed silicon nitride layer in an ineffective attempt to create tensile strain in the thin top (surface) silicon layer. The Wristers patent does not in fact induce effective strain in the top semiconductor layer. The process described in the Wristers patent, forms a BOX structure including a layer of compressively stressed silicon nitride and the final device structure includes the BOX structure positioned between an active region and a substrate. However, the compressively stressed silicon nitride layer is continuous (uninterrupted) in the plane of the wafer and so cannot expand or contract laterally from the as-formed configuration. There is no opportunity for edge relaxation of the buried stressed silicon nitride layer and as such the Wristers patent provides no mechanism for inducing strain in the silicon active region or for relaxing the compressively stressed buried silicon nitride layer.
U.S. Patent Publication No. 2009/0278201 to Chatty, et al., describes strained channel MOSFET devices on SOI wafers. The starting point is a wafer with a buried silicon oxide layer (BOX) on a substrate, with a silicon nitride layer above that and a surface active silicon layer in which MOSFETs will be constructed. This silicon nitride layer may be deposited in a state of compressive or tensile stress up to a maximum magnitude of 200 MPa. From this starting point, isolation trenches are cut through the active silicon layer and the silicon nitride layer underneath it, but stop at the BOX. Then some of the source and drain silicon in the active layer is removed and replaced with a compressive or tensile stressed material (e.g. silicon germanium or silicon:carbon respectively) so as to induce longitudinal compressive or tensile strain in the channel region of the MOSFET. Instead of obtaining significant strain in the channel region from edge relaxation and expansion of the silicon nitride layer, in the Chatty publication, the primary method of inducing strain in the channel region is the well known “embedded source/drain stressor” method. The Chatty publication focuses on using a buried silicon nitride layer as a stiffener against which the force of an embedded stressor in source/drain regions can react to create the desired strain in the channel region. The publication explains that if there is no source/drain embedded stressor present, measurements show that there is no difference in the stress in the channel either when (1) the silicon nitride stiffening layer is present or (2) the silicon nitride stressor is not present. It is clear, therefore, that the Chatty publication does not attempt to induce stress in the channel by the use of a buried silicon nitride stressor together with edge relaxation.